// 请实现对（1011001）2的序列检测功能，模块每拍并行输入2bit，且顺序为高位先输入，当检测到序列，输出一拍高电平脉冲。

module top(
           input clk,
           input rst_n,
           input [1: 0] data_in,
           output reg valid
       );

parameter idle = 4'd0;
parameter s10 = 4'd1;
parameter s1011 = 4'd2;
parameter s101100 = 4'd4;


reg [3: 0] state, next_state;

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			state <= idle;
		else
			state <= next_state;
	end

always@( * )
	begin
		if (!rst_n)
			next_state <= idle;
		else
			case (state)
				idle:
					begin
						next_state = (data_in == 2'b10) ? s10 : idle;
					end
				s10:
					begin
						next_state = (data_in == 2'b11) ? s1011 : (data_in == 2'b10) ? s10 : idle;
					end
				s1011:
					begin
						next_state = (data_in == 2'b00) ? s101100 : (data_in == 2'b10) ? s10 : idle;
					end
				s101100:
					begin
						next_state = (data_in == 2'b11) ? idle : (data_in == 2'b10) ? s10 : idle;
					end
			endcase
	end


always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			valid <= 1'b0;
		else if (state == s101100 && data_in[1])
			valid <= 1'b1;
		else
			valid <= 1'b0;
	end
endmodule
